# Really simple Makefile example
#
# Comment lines begin with #
# VARIABLE=value assignments, sort of like #define in C/C++

# The executable program we want to build is called "hello"
# (PROG is just an arbitrary variable name)
PROG=escape

# The object files needed to build our executable
OBJS=main.o map.o

# Compiler flags; this gives maximum debugging information
CFLAGS=-g -Wall -Werror

# Additionally, you can define the variables when you invoke "make"
# For example "make hello CFLAGS=-g -Werror -Wall" replaces CFLAGS when executing

# If we just say "make", the first target in the file gets built;
# for now it is just a single executable (but by having a
# separate target named "all" we can other things to it later,
# such as running test cases automatically.
all:	$(PROG)

# Here we say that our executable "depends" on our object files;
# in other words, if the object files change, the executable
# needs # to be rebuilt.  Make has some implicit rules for common
# tasks # like building ".o" object files from ".cc" source files,
# so it is not always necessary to specify every step.
$(PROG):	$(OBJS)
	$(CXX) $(CFLAGS) -o $(PROG) $(OBJS)

# This only gets run if the command is "make clean";
# this will # delete all the binary files (executable and objects)
clean:
	rm $(PROG) $(OBJS)

# This only gets run if the command is "make submit";
# this is used to gather all of your files into a submission tarball
submit:
	tar -zcf submit.tar.gz *.cpp *.h Makefile *.txt